PhD in Computer Engineering

There is a growing demand for high-throughput and low-power signal processing in implantable devices. Traditional DSP engines struggle with this need, while compact AI models can offer better accuracy with smaller code sizes. Efficient implementation on silicon can allow small components to run effective machine learning algorithms with minimal power use. The project has the following three objectives:  1. To architect and prototype network topologies tailored to large-scale deep learning driven signal processing algorithms. Novel topologies are supposed to provide load-aware distributed processing on the network, while enabling sustainable energy management. 2. To implement and validate the operation of the introduced networks using FPGA. This step further helps translation of a FPGA design on silicon in a specific complementary metal-oxide-semiconductor (CMOS) technology (e.g. 180 nm). 3. To benchmark energy, performance and accuracy against the state-of-the-arts. Our interest is to develop designs utilizing the previous steps for real-time and on-chip classification of biomedical signals, however, other applications can be identified. For example, we have already developed complex algorithms for implantable brain-computer interfaces that can be translated into hardware using the proposed flow for low-power and sustainable uses.