PhD in Microelectronic Engineering

This fully funded PhD investigates low‑power, high‑reliability chiplet physical‑layer design in advanced CMOS/FinFET technologies, including transceiver optimisation, reliability‑aware subsystems, interposer development, and electrical characterisation./nThe project includes full physical design and ASIC tapeout of chiplet prototypes, supported by industry-linked soclabs./nResearch topics explicitly mentioned include design and optimisation of serial transmitters and receivers, monitoring and control subsystems in the PHY for reliability and performance optimisation, physical design, tapeout and post-silicon characterisation of chiplets in finFET nodes, design and optimisation of interposers, and electrical characterisation of interposers and chiplet systems./nProject is in collaboration with soclabs at the University of Southampton and involves work with industry engineers and CMOS fabrication nodes.